发明名称 |
Methods and apparatus for multi-processing execution of computer instructions |
摘要 |
A multi-processing computer architecture and a method of operating the same are provided. The multi-processing architecture provides a main processor and multiple sub-processors cascaded together to efficiently execute loop operations. The main processor executes operations outside of a loop and controls the loop. The multiple sub-processors are operably interconnected, and are each assigned by the main processor to a given loop iteration. Each sub-processor is operable to receive one or more sub-instructions sequentially, operate on each sub-instruction and propagate the sub-instruction to a subsequent sub-processor.
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申请公布号 |
US2003177343(A1) |
申请公布日期 |
2003.09.18 |
申请号 |
US20020202355 |
申请日期 |
2002.07.24 |
申请人 |
SONY COMP EMTERTAINMENT US |
发明人 |
MAGOSHI HIDETAKA |
分类号 |
G06F15/80;G06F9/00;G06F9/32;G06F9/38;G06F15/00;G06F15/78;(IPC1-7):G06F9/00 |
主分类号 |
G06F15/80 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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