发明名称 Clock signal synthesizer with multiple frequency outputs and method for synthesizing clock signal
摘要 A method for synthesizing a clock signal with multiple frequency outputs for use in a converter for converting a non-interlacing scan data into an interlacing scan data is disclosed. The converter provides a first reference clock signal with a frequency F1. The method includes the steps of receiving the first reference clock signal with the frequency F1 to generate and output a clock signal with a frequency F1xN, proceeding a divided-by-P1 and a divided-by-P2 operations on the clock signal with a frequency F1xN, respectively, to output a first output clock signal with a frequency F1xN/P1 and a second output clock signal with a frequency F1xN/P2, respectively. The value P2/P1 correlates to a ratio of the pixel number of a horizontal scan line in the non-interlacing scan data to that in the interlacing scan data. In addition, a clock signal synthesizer with multiple frequency outputs is also disclosed.
申请公布号 US2003174245(A1) 申请公布日期 2003.09.18
申请号 US20020231847 申请日期 2002.08.30
申请人 VIA TECHNOLOGIES, INC. 发明人 LEE CHUAN-CHEN;TAI CHIA-LIANG;HUANG YI-CHIEH
分类号 H04N5/06;H04N5/44;H04N9/64;(IPC1-7):H04N11/20 主分类号 H04N5/06
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