| 摘要 |
A transmission interval counter measures the period of a packet sync generated in a sync generator. A comparator compares the period of the packet sync to a reference interval as selected by a type selector to calculate a period error. A correction value calculator calculates a correction value based on the period error. An adder sums the correction value to a predetermined value to output a sum. A frequency dividing counter counts the high-speed clock signals to output its count, and is reset by a pulse. A comparator outputs the pulse when the count coincides with the sum. A PCMCLK circuit generates clocks (PCMCLK) synchronized with the pulses. A PCMSYNC circuit frequency-divides the clocks (PCMCLK) by 1/8 to generate synchronization signals (PCMSYNC).
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