SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE FOR HIGH FREQUENCY OPERATION

摘要

A synchronous semiconductor memory device for high frequency operation is provided to perform latency control operation stably at the high frequency operation, by increasing sampling margin in an output control signal generation part. According to a synchronous semiconductor memory device, an output control signal generation part(320) generates a delayed internal clock signal by delaying an N-divided internal clock signal, first and second sampling clock signals delaying the internal clock signal, a first output control clock signal dividing the internal clock signal and controlling to output data by being synchronized with an external clock signal, and an output control signal corresponding to a signal delaying a read information signal as much as time according to CAS latency in response to a CAS latency signal. A data output buffer(355) outputs internal data by buffering the internal data, in response to the output control signal and the first output control clock signal.