发明名称 CDMA chip synchronization circuit
摘要 <p>A CDMA chip synchronization circuit is provided for a mobile communications system employing a wide band CDMA method, especially direct spread code division multiple access (DS-CDMA) method, and is designed to have a capability to certainly perform detection of multipath receiving timing, particularly synchronous tracking, under a low Eb/No environment where multipaths are received in an overlap manner. Herein, a radio receiver (101) converts radio frequency signals to digital base band signals, whilst a search section (111) detects receiving timing with respect to multipath components contained in the digital base band signals. The detected receiving timing is used as a center position for receiving on a time axis. The radio receiver is connected with multipath receivers (112), each of which contains a number of correlators (102) which produce correlation values between the multipath components and dc-spreading codes which are delayed by different delay times respectively. Herein, the correlators correspond to prescribed intervals of time which deviate from the center position for receiving on the time axis. Correlator outputs are temporarily stored in a memory (103). Then, the multipath receiver selects a correlator output having a best receiving quality from among the correlator outputs by every prescribed interval of time corresponding to a pilot period, so synchronous detection is performed using the selected correlator output. Outputs of the multipath receivers are combined at a maximum ratio, so that receiving data are produced. <IMAGE></p>
申请公布号 EP0848503(B1) 申请公布日期 2003.09.17
申请号 EP19970121342 申请日期 1997.12.04
申请人 NEC CORPORATION 发明人 SATO, TOSHIFUMI
分类号 H04J13/00;H04B1/7085;H04B7/26;H04L7/00;H04W56/00;(IPC1-7):H04B1/707 主分类号 H04J13/00
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