| 摘要 |
A ballast circuit including a power factor correction circuit with an alterable d.c. bus charging rate is provided. The power factor correction circuit selectively alters the d.c. bus charging rate such that, during a startup period for the ballast circuit, the charging rate is faster than during a steady-state period. The ballast circuit including a bridge rectifier, a power factor correction circuit, a bus capacitor, and at least one inverter. The power factor correction circuit including a power factor controller, a semiconductor switch operationally coupled to an output signal of the power factor controller, a selectively alterable impedance network operationally coupled to an output of the semiconductor switch and operationally coupled to an input signal of the power factor controller, and an impedance network control circuit operationally coupled to the impedance network to selectively alter the impedance network.
|
