发明名称 |
Information processing apparatus and method and distribution medium |
摘要 |
It is an object to save a circuit scale and simultaneously improve sync-byte pattern detecting performance. A Viterbi detecting circuit executes first the detecting operation without relation to time limitation. A sync-byte detecting circuit detects the sync-byte from the detection result supplied from a path memory built in the Viterbi detecting circuit and also outputs the detected signal to switches and Viterbi detecting circuit in the timing to start detection of user data. The Viterbi circuit initializes (resets) the path memory and path metric corresponding to the detected signal supplied from the sync-byte detecting circuit and also starts subsequently the trellis Viterbi detection accompanied by the time limitation of the trellis path to the data supplied from the switch.
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申请公布号 |
US6622280(B1) |
申请公布日期 |
2003.09.16 |
申请号 |
US19990257861 |
申请日期 |
1999.02.26 |
申请人 |
SONY CORPORATION |
发明人 |
HIGASHINO SATORU |
分类号 |
G11B20/10;G11B20/14;G11B20/18;H03M13/23;H03M13/33;H03M13/41;H04L25/08;(IPC1-7):H03M13/33 |
主分类号 |
G11B20/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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