发明名称 |
Timing verification method employing dynamic abstraction in core/shell partitioning |
摘要 |
A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.
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申请公布号 |
US6622290(B1) |
申请公布日期 |
2003.09.16 |
申请号 |
US20000678150 |
申请日期 |
2000.10.03 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
GINETTI ARNOLD;HAHN MARK STEVEN;KRIPLANI HARISH;AWAD NASER |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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