| 摘要 |
A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit. The system also includes an efficient return channel to minimizine the amount of data transfer bandwidth required in returning status information on the FIFO buffer of the input/output unit. The system also includes an efficiently invoked timer mechanism for temporarily suspending the processor from transmitting stores to the input/output unit when the input/output unit and/or the intermediate devices are congested. The processor is not interrupted by an interrupt request until after the timer mechanism times out, allowing the system an opportunity to clear its congestion before a lengthily invoked interrupt is required.
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