| 摘要 |
A method for implementing segmented digital-analog converters (DACs) operating in the current mode matches the time constants in the most-significant-bit (MSB) segments to the time constants in the (LSB) least-significant-bit segments, and any intermediate-significant-bit (ISB) segments. The method can be implemented using the simple addition of capacitances or the resizing of transistors in the circuit at appropriate points. The resulting DAC exhibits high dynamic linearity and spurious free dynamic range (SFDR).
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