Method for forming sub-critical dimension structures in an integrated circuit

摘要

A method is provided for fabricating a device, which includes device components and spacings that may each have a final dimension that is smaller than a minimum dimension obtainable by a photolithography process used to form the device components. In particular, the method may include patterning an upper layer of the semiconductor topography using the photolithography process to form a device mask having dimensions substantially equal to or greater than the minimum dimension. The method may further include trimming the device mask and forming a semiconductor structure in alignment with the trimmed device mask. In addition, the method may include patterning the semiconductor structure to form device components and spacings therebetween. In general, patterning the semiconductor structure may include tapering a first layer of the semiconductor structure and removing an exposed portion of a second layer of the semiconductor structure.