发明名称 |
Random logic circuit |
摘要 |
A random logic circuit comprises an input portion for inputting data; a first latch portion for receiving the data outputted from the input portion, and holding and outputting the data; a second latch portion for receiving the data outputted from the first latch portion, and holding and outputting the data; an output portion for receiving the data outputted from the second latch portion and outputting the data to a logic circuit; and a prevention circuit for preventing generation of a sub-threshold leak current in sleep mode between the first latch portion and the second latch portion.
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申请公布号 |
US6621306(B2) |
申请公布日期 |
2003.09.16 |
申请号 |
US20020036406 |
申请日期 |
2002.01.07 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OOISHI TSUKASA;HIDAKA HIDETO |
分类号 |
H03K19/20;H03K3/012;H03K3/356;H03K3/3562;H03K19/0944;(IPC1-7):H03K19/094 |
主分类号 |
H03K19/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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