| 摘要 |
A shift register has m stages which store one of two states, where m is an integer more than 1, each stage including clock input terminals at which n-phase clock signals are input, where n is an integer more than 1, and an input terminal, and an output terminal. The input terminal of one stage receives the signal delivered from an input terminal of the shift register or from the output terminal of the previous stage. The signal output at the output terminal of one stage is passed to the input terminal of the subsequent stage or to an output terminal of the shift register. Each stage receives an initial state level from one of the clock input terminals. The initial state level is used to initialize the state of each stage.
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