| 摘要 |
An output circuit (6) of a DRAM (semiconductor storage device) is provided with a refresh monitor circuit which is substantially composed of a NAND gate (NA1), an AND gate (A1), Pch-Tr2 and Nch-Tr4. The TMSELF signal (test mode signal) and the int. ZRAS signal (internal signal for provoking a refreshing action) are inputted into the refresh monitor circuit. The refresh monitor circuit outputs a monitoring signal, which has a wave form as same as that of the int. ZRAS signal, to an output node (DQ) of the output circuit (6), when the TMSELF signal has become H during the self refresh process. The refresh monitor circuit can monitor the int. ZRAS signal on the basis of the monitoring signal.
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