发明名称
摘要 The multi-port cache memory of the present invention is formed by using, as constituents, one-port cell blocks (2,5) adapted for a large storage capacity, making it possible to easily provide a multi-port cache memory of a large storage capacity and reduced integration area, which has a large random access bandwidth, is capable of parallel access from a plurality of ports, and is adapted for use in advanced microprocessors having a small cache miss probability.
申请公布号 KR100397413(B1) 申请公布日期 2003.09.13
申请号 KR20010048243 申请日期 2001.08.10
申请人 发明人
分类号 G06F12/08;G11C11/41 主分类号 G06F12/08
代理机构 代理人
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