发明名称 NON-INTEGRAL MULTIPLE SIZE ARRAY LOOP PROCESSING IN SIMD ARCHITECTURE
摘要 A method of controlling the enabling of processor datapaths in a SIMD processor during a loop processing operation is described. The information used by the method includes an allocation between the data items and a memory, a size of the array, and a number of remaining parallel passes of the datapaths in the loop processing operation. A computer instruction is also provided, which includes a loop handling instruction that specifies the enabling of one of a plurality of processor datapaths during processing an array of data items. The instruction includes a count field that specifies the number of remaining parallel loop passes to process the array and a count field that specifies the number of serial loop passes to process the array. Different instructions can be used to handle different allocations of passes to parallel datapaths. The instruction also uses information about the total number of datapaths.
申请公布号 KR20030072354(A) 申请公布日期 2003.09.13
申请号 KR20037006484 申请日期 2003.05.13
申请人 发明人
分类号 G06F9/40;G06F9/32;G06F9/345;G06F9/38;G06F13/16;G06F15/16;G06F15/80 主分类号 G06F9/40
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