| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To simplify clock wiring by reproducing a sampling clock for accurately extracting data synchronously with a serial data input to thereby eliminate risk of omission of the reproduction of received data after the value of received data is not transient for a long time. <P>SOLUTION: The clock generation circuit is provided with a plurality of data rate delay circuits 10 and a logic circuit 20. In the circuits 10, each circuit is cascade connected as a whole, the serial datas is inputted to the first stage circuit while being branched, the circuit of each stage delays the inputted data by the data rate of the serial data input and outputs one pulse signal deviated from the input data by the 1/n (integer) period of the data rate for each of bit data of the serial data input. The logic circuit 20 for outputting the sampling clock for extracting data from the serial data input by ORing the pulse signals respectively outputted from the plurality of data rate delay circuits. <P>COPYRIGHT: (C)2003,JPO</p> |
