发明名称 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device structure capable of reducing the probability of the generation of any failure by reducing the number of masks and reducing the number of processes, and to provide a method for manufacturing a semiconductor device structure capable of determining a source (drain) electrode pattern position for a source (drain) area like self-alignment. <P>SOLUTION: The dope silicon layer of source/drain wiring materials is formed and then etched so that a source/drain electrode and a gate electrode can be simultaneously formed. Then, dopant impurity is thermally diffused from the source/drain electrode to the source/drain area by heat treatment so that an ohm contact junction can be formed, and that the source/drain area can be formed as a first conductive low sheet resistor. <P>COPYRIGHT: (C)2003,JPO</p>
申请公布号 JP2003257989(A) 申请公布日期 2003.09.12
申请号 JP20020052814 申请日期 2002.02.28
申请人 SEMICONDUCTOR ENERGY LAB CO LTD 发明人 ARAO TATSUYA
分类号 G02F1/1368;H01L21/20;H01L21/265;H01L21/28;H01L21/285;H01L21/3205;H01L21/336;H01L21/768;H01L23/52;H01L29/786;(IPC1-7):H01L21/336;G02F1/136;H01L21/320 主分类号 G02F1/1368
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