发明名称 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a CMP method by which the enhancement of throughput and the maintenance of flatness are compatible. SOLUTION: This method predicts by simulations an optimum polishing time in CMP and measuring a location where surface irregularities of a wafer are measured, and based on this result, the wafer is polished by the CMP. After the CMP, the surface irregularities are measured by a measuring means, and simulation parameters are changed so as to agree with the measurement. By using the simulation parameters, the optimum polishing time and the candidate measuring location on the wafer subsequently polished are predicted. This method makes the enhancement of throughput and the maintenance of flatness compatible. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003257915(A) 申请公布日期 2003.09.12
申请号 JP20020056725 申请日期 2002.03.04
申请人 HITACHI LTD 发明人 OTAKE ATSUSHI;KOBAYASHI KINYA;ARAI TOSHIYUKI;KAWASAKI TAKAHIKO
分类号 H01L21/768;H01L21/02;H01L21/304;H01L23/522;(IPC1-7):H01L21/304 主分类号 H01L21/768
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