发明名称 METHOD FOR FORMING VIAHOLE
摘要 PROBLEM TO BE SOLVED: To provide a method for forming a viahole for eliminating the imperfect connection of a viahole metal with upper layer metal wiring formed on the viahole metal. SOLUTION: Baking is applied to a resist in a viahole aperture, thereby making the edge angle of the resist obtuse in such a manner that an angle between an resist sidewall surface and an interlayer insulating film surface becomes 45-75°. In this state, a metal is embedded in the viahole. Before the metal is embedded in the viahole, the resist on the interlayer insulating film is retreated in the horizontal direction by a single side of 0.1-0.3μm, and the thickness of the resist is made 0.5-1.0μm by using oxygen plasma. As a result, a metal form of a nearly square via-contact is obtained, so that it is made possible to eliminate the imperfect connection of the viahole metal with the metal wiring layer formed on the viahole metal. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003257973(A) 申请公布日期 2003.09.12
申请号 JP20020057985 申请日期 2002.03.04
申请人 SUMITOMO ELECTRIC IND LTD 发明人 KOTANI KENJI;TOSAKA YASUHIRO
分类号 G03F7/20;H01L21/027;H01L21/28;H01L21/3205;H01L21/768;(IPC1-7):H01L21/320 主分类号 G03F7/20
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