发明名称 METHOD FOR FORMING TRANSISTOR MODEL AND METHOD FOR DESIGNING ELECTRONIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method for forming a transistor model which makes it possible to obtain a model accurately representing low-frequency noise of a MOS transistor. SOLUTION: A semiconductor manufacturing process of obtaining an electronic circuit to be designed is used to manufacture a plurality of MOS transistors of representative device sizes by way of trial (S1). The intensity of drain current noise of a specified low frequency that each transistor generates in it saturation area is measured while a drain voltage has a specified value and a gate voltage is varied (S2). The intensity of drain current noise of the same frequency that the transistor generates in its linear area is measured (S2) while the drain voltage is varied. According to measured drain current noise intensities, model expressions of the respective drain current noise intensities that the transistors generate in their saturation areas and linear areas are derived (S4, S5). According to the derived model expression, a database is created and stored in a storage medium (S6, S7). COPYRIGHT: (C)2003,JPO
申请公布号 JP2003258100(A) 申请公布日期 2003.09.12
申请号 JP20020056140 申请日期 2002.03.01
申请人 ASAHI KASEI MICROSYSTEMS KK 发明人 TOITA MASATO;AKABOSHI TOMOYOSHI
分类号 G06F17/50;H01L21/82;(IPC1-7):H01L21/82 主分类号 G06F17/50
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