| 摘要 |
PROBLEM TO BE SOLVED: To provide a design method of a semiconductor integrated circuit device, design equipment and a design program wherein the influence of propagation delay fluctuations which is generated by process irregularities can be restrained. SOLUTION: The ratio of the sum total of gate input load capacitance to wiring capacitance of a path from a signal input terminal (source) as far as a signal output terminal (sink) the terminals of which are positioned on the same net is calculated as process irregularity sensitivity, concerning capacitance component of the path from the objective source to the sink. Wiring capacitance load is adjusted in a path, wherein the process irregularity sensitivity concerning capacitance component is higher than a reference value, the process irregularity sensitivity concerning capacitance component of the path is reduced, and the process irregularity sensitivity concerning capacitance component of each of the paths is optimized, in such a manner that the process irregularity sensitivity concerning capacitance component of all the paths becomes at most the reference value. COPYRIGHT: (C)2003,JPO
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