发明名称 |
Multidispatch cpu integrated circuit having virtualized and modular resources and adjustable dispatch priority |
摘要 |
A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address execution pipelines and floating point execution pipelines. Each instruction decode and dispatch unit requests resources needed to perform an instruction of the resource allocation unit, which arbitrates among the multiple instruction decode and dispatch units.
|
申请公布号 |
US2003172250(A1) |
申请公布日期 |
2003.09.11 |
申请号 |
US20020092714 |
申请日期 |
2002.03.06 |
申请人 |
FETZER ERIC S.;KEVER WAYNE;DELANO ERIC |
发明人 |
FETZER ERIC S.;KEVER WAYNE;DELANO ERIC |
分类号 |
G06F9/38;(IPC1-7):G06F9/00 |
主分类号 |
G06F9/38 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|