Built-in self test parallel JTAG serial chain architecture for reduced test vector size

摘要

A system and method for programming built-in self-testing (BIST) state machines to test integrated circuit components are disclosed. The standard Joint Test Action Group method for programming BIST state machines is modified to increase speed and efficiency. The registers containing the instructions for BIST testing are connected in parallel, as opposed to the standard serial connections, allowing the registers to be fed instructions simultaneously. This cuts down the required time to feed test instructions to the BIST state machines. The addition of multiple shadow registers to each register further cuts down the required time to feed test instructions to the BIST state machines.