| 摘要 |
A method and apparatus for accessing data elements of an N-element data block on N memory locations distributed over Q memory modules via Q parallel accesses. The Q memory modules are addressable in a q-bit module address and an (n-q) bit row address in a power-of-two stride fashion. The row address is selected from (n-q) bits of the index address, and the module address for one of the Q accesses is obtained from bitwise exclusive-OR operation on bits obtained from corresponding positions in a plurality of q-bit fields grouped from the index address.
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