| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock jitter leveling circuit for reducing the jitter of a clock signal in a synchronous information processor for operating synchronously with the clock signal, a clock jitter leveling method using this circuit, and a module incorporated with the clock jitter leveling circuit, and capable of coping with a speed increase. <P>SOLUTION: A clock buffer 4, the clock jitter averaging circuit 5, a clock buffer 6, and an internal circuit 7 are arranged in the respective modules 3 of the synchronous information processor, and are connected in series in this order. A clock n pulse period detecting circuit 8 and a frequency n gradually doubling circuit 9 are arranged in the clock jitter leveling circuit 5. The clock n pulse period detecting circuit 8 detects a period equivalent to a continuous n wave length in the clock signal a, and forms a pulse waveform equivalent to one period from a waveform equivalent to this n period, and outputs the pulse waveform as a pulse signal b. The frequency n gradually doubling circuit 9 uniformly divides one period of the pulse signal b into n periods, and forms a pulse signal c. <P>COPYRIGHT: (C)2003,JPO |
