| 摘要 |
<p>When data is transmitted from a main unit of an apparatus 11 to an IC card 12, a clock signal is input to a clock input of FF2R through a path of (buffer CK1S -> transmission path CLK -> buffer CK2R). A data signal is output from FF1S in synchronization with a leading edge of the clock signal. The data signal is input to a data input of FF2R through a path of (buffer 101S -> transmission path DATA -> buffer 102R). Thereafter, the data signal is captured. When data is transmitted from the IC card 12 to the main body 11, a clock signal is input to a clock input of FF1R through a path of (buffer CK2S -> transmission path CLK -> buffer CK1R). The data signal is output from FF2S in synchronization with a leading edge of the clock signal. The clock signal is input to a data input of FF1R through a path of (buffer 102S -> transmission path DATA -> buffer 101R). Thereafter, the data signal is captured. <IMAGE></p> |
