| 摘要 |
PROBLEM TO BE SOLVED: To solve such a problem that restriction is set on a termination address when block repeat instructions for executing an instruction set multiple times overlap with the other, in instruction execution of a digital processor. SOLUTION: A conditional branch circuit is formed behind an instruction decoder. When a start instruction of a succeeding block repeat 1 instruction is issued during execution of a preceding block repeat 0 instruction, the values of both termination addresses DOEND0 and DOEND1 are compared with each other, and in the case of DOEND0<DOEND1, the succeeding block 1 repeat instruction is disabled to prevent its execution. When the succeeding block repeat 1 instruction is received during execution of the last cycle of the preceding block 0 instruction, it is executed. COPYRIGHT: (C)2003,JPO
|
