Method and architecture for reducing the power consumption for memory devices in refresh operations

摘要

A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) enabling the background operations in one or more sections of the memory array when one or more control signals are in a first state and disabling the background operations in one or more sections of the memory array when the one or more control signals are in a second state and (ii) generating the one or more control signals in response to an address signal.