发明名称 |
Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors |
摘要 |
A method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extension (SDE) adjacent the conductive gate structure. The method also includes forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.
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申请公布号 |
US6617219(B1) |
申请公布日期 |
2003.09.09 |
申请号 |
US20010784628 |
申请日期 |
2001.02.15 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
DUANE MICHAEL P.;WU DAVID D.;AMINPUR MASSUD;LUNING SCOTT D. |
分类号 |
H01L21/265;H01L21/336;H01L29/10;H01L29/78;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/265 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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