CLOCKING FOR PIPELINED ROUTING

摘要

An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

主权项

1. An integrated circuit, comprising:
a first clock selection stage that selects from a first plurality of clock signals and that outputs a second plurality of clock signals; a second clock selection stage that selects from the second plurality of clock signals that and that outputs a third plurality of clock signals; and pipelined routing resources that receive the third plurality of clock signals.