| 摘要 |
The interleaving/deinterleaving processing is executed in one machine cycle in which input data is arranged and stored at storage areas with contiguous addresses in RAM 103, the stored data is read with two times the accuracy in the order of address in RAM 103 corresponding to an address from first pointer 101 and an address front address generator 102, and one item of the read data is stored at a storage area with an even address in RAM 110 using an address from second pointer 106 and an address from address generator 107, while the other item of the read data is stored at a storage area with an odd address a predetermined value away from the even address in RAM 110 using an address from third pointer 108 and an address from address generator 109. It is thereby possible to achieve miniaturization, one-chip structure and cost reduction in a DSP and further achieve low power consumption battery, light-weighting, and cost reduction in a portable terminal device. <IMAGE> |
