Integrated circuit having receiver jitter tolerance (“JTOL”) measurement

摘要

An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

主权项

1. An integrated circuit, comprising:
circuitry to sample an input signal according to a sampling clock, to generate data samples; a clock source to generate the sampling clock; circuitry to compare expected data values with the data samples and to generate an error indication in dependence on whether the expected data values match the data samples; and circuitry to inject jitter into the sampling clock to simulate jitter in the input signal; wherein the clock source comprises a clock recovery circuit operable to generate a recovered clock in dependence on transitions in the input signal, the sampling clock being dependent on the recovered clock.