| 摘要 |
Problems are prevented that a refresh provides an influence to a normal access and that a continuation of write operations inhibits refresh. <??>In a semiconductor memory device, a clock signal providing a reference to a time interval of refresh operations based on addresses corresponding to a single row is generated as a refresh clock signal. A transition of an access address "Address" externally supplied and corresponding to a memory cell is detected, so that a refresh operation is executed to a memory cell corresponding to a refresh address by triggering the generation of this detection signal before an access to a memory cell designated by the access address is made, wherein upon the input of a write enable signal /WE, the refresh is executed by triggering this signal before a write operation is executed and the refresh operation by triggering the generation of the access address is discontinued in a predetermined period of time based on the refresh clock signal. <IMAGE>
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