发明名称 BOOSTING POTENTIAL GENERATING CIRCUIT AND CONTROL METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a boosting potential generating circuit in which high speed operation can be performed in a semiconductor memory, while miniaturization also can be performed, even if external power source voltage is dropped in a semiconductor memory. <P>SOLUTION: In a boosting potential generating circuit provided with a capacitive MOS transistor and a transfer MOS transistor and used for a DRAM comprising memory cells, a boosting potential generating circuit of small area and large capacitance can be realized by making a gate insulation film of the capacitive MOS transistor a thinner film than a gate insulation film of a MOS transistor constituting a memory cell. In this case, it is preferable that thickness of a gate insulation film of the transfer MOS transistor is made the same as or thicker than that of the capacitive MOS transistor. <P>COPYRIGHT: (C)2003,JPO
申请公布号 JP2003249076(A) 申请公布日期 2003.09.05
申请号 JP20020044533 申请日期 2002.02.21
申请人 ELPIDA MEMORY INC;HITACHI ULSI SYSTEMS CO LTD;HITACHI LTD 发明人 NARUI SEIJI;MAE KENJI;MORINO MAKOTO;KUBONAI SHUICHI
分类号 G11C11/407;G11C5/14;G11C11/4074;H01L21/822;H01L21/8242;H01L27/04;H01L27/10;H01L27/108;H02M3/07 主分类号 G11C11/407
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