发明名称 EVALUATION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide an evaluation circuit capable of performing evaluation in a state close to actual operation at the evaluation of LSIs and to reduce the size of a testing circuit. <P>SOLUTION: The LSI evaluation circuit for monitoring signals inside the LSIs, connected to an AGP bus comprises both a register for setting test mode and normal mode and a selector for switching between a signal for the monitoring and a normal signal, according to the setting of the register. Signals from the selector are outputted to the AGP bus, and data inside the LSIs, after data transfer buffering using a strobe, are outputted to an SBA terminal without making them stored in a lead buffer. <P>COPYRIGHT: (C)2003,JPO
申请公布号 JP2003248034(A) 申请公布日期 2003.09.05
申请号 JP20020048302 申请日期 2002.02.25
申请人 NEF:KK 发明人 FUJIWARA YUICHI
分类号 G01R31/28;G01R31/317;G01R31/3185;G06F11/22 主分类号 G01R31/28
代理机构 代理人
主权项
地址