| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a pad layout method for semiconductor chips which can reduce the chip area. <P>SOLUTION: Signal input/output terminals 2 and short-circuiting pads 6 connected to a transparent conductive film 4 are formed on the sides of a semiconductor chip 1. Test terminals 3, for determining characteristics of the chip 1, are disposed inside the short-circuiting pads 6 on the chip 1. This reduces the number of pads disposed on the periphery of the chip 1 and enables the semiconductor chip area to be miniaturized. <P>COPYRIGHT: (C)2003,JPO</p> |
