| 摘要 |
PROBLEM TO BE SOLVED: To improve data read-out margin in a semiconductor memory having memory cells constituted of variable capacitors. SOLUTION: A plurality of memory cell arrays are provided with a memory cell constituted of a variable capacitor and a bit wire while the arrays are operated with mutually different timings. The bit wires for respective memory cell arrays are connected to the bit wire of the other memory cell array by a connecting wire. According to this arrangement, actual capacitance of the bit wire becomes a value wherein the capacitance of the connecting wire and the capacitance of the bit wires for other memory arrays are added. Accordingly, the changing amount of a voltage in the bit wire due to the division of capacitance can be increased. As a result, the prevention of the deterioration of the read-out margin and the prevention of deterioration of the manufacturing yield of the semiconductor memory are permitted. The changing amount of voltage in the bit wire is increased whereby the read-out time of data can be shortened. COPYRIGHT: (C)2003,JPO
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