| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which abnormality of the pulse width of a read-pulse can be satisfactorily detected. <P>SOLUTION: Transition to the prescribed potential in a dummy cell section 20a is delayed to the preceding prescribed timing from the timing of the prescribed edge of the read-pulse when the read-pulse has the prescribed pulse width, and when the pulse width of the read-pulse is varied and transition for the prescribed potential is delayed more than the timing of the prescribed edge, an error output circuit 317 generates an error detection signal. Also, transition to the prescribed potential in a dummy cell section 20a is delayed to the subsequent prescribed timing from the timing of the prescribed edge of the read-pulse when the read-pulse has the prescribed pulse width, and when the pulse width of the read-pulse is varied and transition for the prescribed potential is made before the timing of the prescribed edge, an error output circuit 318 generates an error detection signal. <P>COPYRIGHT: (C)2003,JPO</p> |
