| 摘要 |
<P>PROBLEM TO BE SOLVED: To verify locking operation by operating a PLL by the same frequency as that at actual operation, even when the maximum output clock frequency of a low-speed and general-purpose tester is lower than the frequency of the reference clock of the PLL in actual operation. <P>SOLUTION: This PLL testing circuit is provided with a frequency divider for dividing the frequency of an internal clock outputted from the PLL and outputting a frequency-divided clock, an output switch for selectively outputting the internal clock outputted from the PLL or the frequency-divided clock outputted from the frequency divider according to a test mode signal, and a frequency-measuring device for measuring the frequency of the internal clock outputted from the PLL and outputting the result of the measurement. As a result this, the PLL is operated at the speed of the actual operation at test mode to measure the frequency of the internal clock outputted from the PLL. By outputting the result of the measurement to the outside, whether the internal clock has a specific frequency is verified easily and externally. <P>COPYRIGHT: (C)2003,JPO |
