| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an integrated circuit which transmits clock signals with little skew and facilitates adjustment of buffers for driving clock wirings. <P>SOLUTION: A plurality of clock wirings 5a, 5b, 5c, 5d are developed radially, starting from one set meeting point 3 on a logical integrated circuit region 1 to transmit a clock signal to logic circuits 7 via the clock wirings 5a, 5b, 5c, 5d. A clock wiring 4, connected to the meeting point 3, has a buffer 6 outside the integrated circuit region 1. A propagation delay measuring circuit is connected to the clock wirings 5b, 5c and is composed of a combination of a first DELAY cell 8a with a monitor input/output part 2a and a combination of a second DELAY cell 8b with a monitor input/output part 2b. <P>COPYRIGHT: (C)2003,JPO</p> |
