| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a memory device in which all power source voltages are generated by one input inverter circuit. <P>SOLUTION: An output circuit 14 of this memory device comprises a bias circuit 40 generating an output depending on power source voltage Vcc, an inverter circuit 35 including a P channel transistor 31 and an N channel transistor 32 in which a common data line CDL is inputted to gates, and a P channel transistor 33 which is connected to the power source voltage Vcc side of the inverter circuit 35 and in which an output of the bias circuit 40 is inputted to a gate. <P>COPYRIGHT: (C)2003,JPO</p> |
