发明名称 PIPELINED MULTI-ACCESS MEMORY APPARATUS AND METHOD
摘要 A memory management system provides the ability for multiple requesters to access blocks of memory in a pipelined manner. During a first clock, requests for one or more of the memory blocks are received by the system. A determination is made of whether one of the memory blocks is requested by one or more requests. If the same memory block is requested by two or more requests, the system performs a further determination of which of the requests will be provided to the memory block. The determined request is provided to the memory block on the first clock. During a second clock, the data of the determined request is latched to the memory block and a memory access is initiated. If the request is a write request, the data is written to the memory block. If the request is a read request, then the requested data is retrieved and, on a third clock, the data is driven onto a bus, routed to the determined requester, and available to be latched into the requester on the fourth clock.
申请公布号 WO0237284(A3) 申请公布日期 2003.09.04
申请号 WO2001US46216 申请日期 2001.11.02
申请人 BROADCOM CORPORATION 发明人 MADAR, LAWRENCE, J., III;NICKOLLS, JOHN, R.;MIRSKY, ETHAN
分类号 G06F12/00;G06F13/16 主分类号 G06F12/00
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