发明名称 |
PROCESSOR INSTRUCTION SET SIMULATION POWER ESTIMATION METHOD |
摘要 |
<p>A plurality of compound Single Instruction/Multiple Data instructions in the form of vector arithmetic unit instructions and vector network unit instructions are disclosed.(S12). Each compound Single Instruction/Multiple Data instruction is formed by a selection of two or more Single Instruction/Multiple Data operations of a reduced instruction set computing type, and a combination of the selected Single Instruction/Multiple Data operations (S14) to execute in a single instruction cycle to thereby yield the compound Single Instruction/Multiple Data instruction.</p> |
申请公布号 |
WO03073270(A1) |
申请公布日期 |
2003.09.04 |
申请号 |
WO2003US01777 |
申请日期 |
2003.01.21 |
申请人 |
MOTOROLA, INC. |
发明人 |
DESAI, VIPUL ANIL;GURNEY, DAVID, P.;CHAU, BENSON;CUTTS, KEVIN M. |
分类号 |
G06F1/32;G06F9/315;G06F9/318;G06F9/38;G06F11/34;G06F17/50;(IPC1-7):G06F9/44;G06F15/00;G06F9/45 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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