发明名称 |
Jitter-detecting circuit, receiving circuit including the jitter-detecting circuit, and communication system |
摘要 |
To provide a method for making a receiving-sensitivity control parameter for deciding the receiving sensitivity of an optical receiving circuit automatically follow the optimum position by using the jitter value of a binary-equalizing-data signal obtained by binary-converting an input signal as a parameter showing the quality of the input signal. A binary-equalizing-data signal output from a limiter amplifier and a clock extracted by a clock-extracting circuit are input to a jitter-detecting circuit. The jitter-detecting circuit outputs a voltage corresponding to the jitter value of the binary-equalizing-data signal. A control circuit receives an output of the jitter-detecting circuit and performs an arithmetic processing by using a DSP or the like, and controls the identification voltage of the limiter amplifier so that the jitter value of the binary-equalizing-data signal (output of jitter-detecting circuit) is minimized.
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申请公布号 |
US2003165207(A1) |
申请公布日期 |
2003.09.04 |
申请号 |
US20030373928 |
申请日期 |
2003.02.25 |
申请人 |
NEC CORPORATION |
发明人 |
NOGUCHI HIDEMI;KOGISO CHIHARU |
分类号 |
H04B10/00;H04L1/20;H04L7/02;H04L25/02;H04L25/03;(IPC1-7):H04L7/00 |
主分类号 |
H04B10/00 |
代理机构 |
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主权项 |
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地址 |
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