| 摘要 |
A CDS circuit (20) is provided with a clamping circuit (21,22) for clamping the output signal of a solid-state imaging device to a signal potential and an S/H circuit (24, 25) for sampling the differential potential between the clamped signal potential and a reference potential. The output signal is clamped to the signal potential by applying a first clamping pulse CP1 before the accumulated charge reset of the solid-state imaging device and applying a second clamping pulse CP2 after the accumulated charge reset so as to sample and hold the differential potential. Thus, the CDS circuit (20) can perform a clamping and a sample-and-hold operation along the stream (stream of time) of the signal outputted from the solid-state imaging device. As a result it is unnecessary to provide any S/H circuit for delaying the signal potential by a predetermined time in the solid-state imaging device.
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