| 摘要 |
A level shifter 3 comprises first and second P-type TFTs 5, 6 and first and second N-type TFTs 7, 8 for latching the levels of first and second output nodes N5, N6, third and fourth N-type TFTs 9, 10 for setting the levels of the first and second output nodes N5, N6, and first and second resistance elements 11, 12 and first and second capacitors 13, 14 for applying a voltage about 6 V higher than the amplitude voltage 3V of an input signal VI between the third and fourth N-type TFTs 9, 10 in response to the fall and rise of the input signal VI.
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