| 摘要 |
PURPOSE: A data communication system is provided to eliminate a load generated at a processor of a system controller by using a clock signal, which is used for a synchronization at a control instructor, as an operating signal, and to speedily check a wrong operation or an abnormal state. CONSTITUTION: The system comprises an interface logic circuit(21), the first shift register(25), the second shift register(27), and a counter(23). The interface logic circuit(21) includes a PPD(Pulse Position Data) terminal which converts a serial control signal and a parallel state signal, and transmits or receives the converted signals, and also includes a clock terminal which receives a clock signal. The first shift register(25) converts a parallel state signal into a serial state signal, and the second register(27) converts a serial control signal into a parallel state signal. The counter(23) counts a communication frequency of the control signal and the state signal.
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