发明名称 Method of fabricating semiconductor device having element isolation trench
摘要 Threshold voltage fluctuation in upper corner portions of a trench isolation is inhibited by rounding upper corner portions of the trench by thermal oxidation, introducing a first impurity into both upper corner portions of the trench and heat-treating the semiconductor substrate. Embodiments include increasing the threshold voltage in the upper corner portion of the trench in an n-channel transistor, previously increased by rounding oxidation, and introducing a p-type impurity, thereby canceling the threshold voltage reduction resulting from diffusion of the impurity during heat-treating the semiconductor substrate. In a p-channel transistor, the threshold voltage in the upper corner portion of the trench is increased by rounding oxidation thereby canceling the threshold voltage reduction resulting from introduction of the p-type first impurity into both upper corner portions of the trench.
申请公布号 US6613635(B2) 申请公布日期 2003.09.02
申请号 US20010015756 申请日期 2001.12.17
申请人 SANYO ELECTRIC CO., LTD. 发明人 ODA MASAHIRO;SASADA KAZUHIRO
分类号 H01L21/762;H01L21/8238;(IPC1-7):H01L21/336 主分类号 H01L21/762
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