发明名称 Method and apparatus for testing a logic device
摘要 Method and apparatus provides for testing a device or system with a pattern generator. A series of predetermined test vectors are stored, and, for at least some of the test vectors, an associated predetermined MISR signature. A test vector is applied to a device or system under test and a gold unit in response to a gating signal, the test vector having an associated MISR determined by simulating the expected result vector. In response thereto, the gold unit and the device or system under test each produce a result vector which are compared to detect errors in the performance of the system or device under test. A MISR signature is generated for the result vector from the gold unit. The MISR signature for the result vector is then compared to the MISR associated with the input test vector. If the signatures do not match, further test vectors are prevented from being applied to the device or system under test. If the signatures match, a gating signal is provided so that additional test vectors are applied to the device or system under test.
申请公布号 US6615379(B1) 申请公布日期 2003.09.02
申请号 US19990457255 申请日期 1999.12.08
申请人 INTEL CORPORATION 发明人 TRIPP MICHAEL J.;ALEXANDER JAMES W.
分类号 G01R31/3185;(IPC1-7):G01R31/28;G01R31/26 主分类号 G01R31/3185
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